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V62C1801024L(L)
Ultra Low Power 128K x 8 CMOS SRAM
Features
* Ultra Low-power consumption - Active: 20mA at 70ns - Stand-by: 5 A (CMOS input/output) 1 A CMOS input/output, L version * Single +1.8V to 2.2V Power Supply * Equal access and cycle time * 70/85/100/150 ns access time * Easy memory expansion with CE1 , CE2 and OE inputs * 1.0V data retention mode * TTL compatible, Tri-state input/output * Automatic power-down when deselected
Functional Description
The V62C1801024L is a low power CMOS Static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW CE1 , an active HIGH CE2, an active LOW OE, and Tri-state I/O's. This device has an automatic power-down mode feature when deselected. Writing to the device is accomplished by taking Chip Enable 1 (CE1 ) with Write Enable (WE) LOW, and Chip Enable 2 (CE2) HIGH. Reading from the device is performed by taking Chip Enable 1 (CE1) with Output Enable (OE) LOW while Write Enable (WE ) and Chip Enable 2 (CE2) is HIGH. The I/O pins are placed in a high-impedance state when the device is deselected: the outputs are disabled during a write cycle. The V62C1801024LL comes with a 1V data retention feature and Lower Standby Power. The V62C1801024L is available in a 32-pin 8 x 20 mm TSOP1 / STSOP / 48-fpBGA packages.
Logic Block Diagram
32-Pin TSOP1 / STSOP (See next page)
A11 A9 A8 A13 WE CE2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2 A3
A0
BUFFER INPUT BUFFER
ROW DECODER ROW DECODER
SENSE AMP SENSE AMP
A1 A1 A2
A2 A3 A4 A3
A5 A4 A6 A5 A7 A6 A8 A7 A9
I/O8
I/O7
A15 Vcc NC A16 A14 A12
1024 1024 X X 1024
1024
I/O1
A7 A6 A5 A4
I/O0
A8
COLUMN DECODER
COLUMN DECODER
A10 A11 A12 A13 A14 A15 A16
CONTROL CIRCUIT
A15 A16
CONTROL CIRCUIT
OE WE OE CE1 WE CE2
A9
A10
A11
A12
A13
A14
CE1 CE2
1 REV. 1.1 April 2001 V62C1801024L(L)
V62C1801024L(L)
MOSEL VITELIC V62C1801024L(L)B
6 5 4 3 2 1
A
B
C
D
E
F
G
H
TOP VIEW
Top View 48-CSP Ball-Grid Array package (shading indicates no ball) 1 A0 I/O4 I/O5 VSS VDD I/O6 I/O7 A9 2 A1 A2 NC NC NC NC OE A10 3 CE2 WE NC NC NC NC CE1 A11 4 A3 A4 A5 NC NC NC A16 A12 5 A6 A7 NC NC NC NC A15 A13 6 A8 I/O0 I/O1 VDD VSS I/O2 I/O3 A14
A B C D E F G H
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REV. 1.1 April 2001 V62C1801024L(L)
V62C1801024L(L)
Absolute Maximum Ratings * Parameter
Voltage on Any Pin Relative to Gnd Power Dissipation Storage Temperature (Plastic) Temperature Under Bias
Symbol
Vt PT Tstg Tbias
Minimum
-0.5 - -55 -40
Maximum
4.6 1.0 +150 +85
Unit
V W
0C 0
C
* Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions outside those indicated in the operational sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect reliability.
Truth Table CE1
H X L L L
CE2
X L H H H
WE
X X H H L
OE
X X L H X
Data
High-Z High-Z Data Out High-Z Data In Standby Standby Active, Read
Mode
Active, Output Disable Active, Write
* Key: X = Don't Care, L = Low, H = High
Recommended Operating Conditions (TA = 00C to +700C / -400C to 850C**) Parameter
Supply Voltage
Symbol
VCC Gnd VIH VIL
Min
1.8 0.0 1.6 -0.5*
Typ
2.0 0.0 -
Max
2.2 0.0 VCC + 0.2 0.4
Unit
V V V V
Input Voltage
* VIL min = -1.0V for pulse width less than tRC/2. ** For Industrial Temperature.
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REV. 1.1 April 2001 V62C1801024L(L)
V62C1801024L(L)
DC Operating Characteristics (Vcc = 1.8 to 2.2V, Gnd = 0V, TA = 00C to +700C / -400C to 850C) Parameter
Input Leakage Current Output Leakage Current Operating Power Supply Current Average Operating Current
Sym
Test Conditions
Vcc = Max, Vin = Gnd to Vcc CE1 = VIH or CE2 = VIL Vcc= Max, VOUT = Gnd to Vcc CE1 = VIL , CE2 = VIH VIN = VIH or VIL , IOUT = 0 mA CE1 = VIL , CE2 = VIH IOUT = 0mA, Min Cycle, 100% Duty CE1 = 0.2V, CE2 = Vcc - 0.2V IOUT = 0mA,
Cycle Time=1s, 100% Duty
-70
1 1 3 25 -
-85
1 1 3 20
-100
1 1 3 15 -
-150
1 1 3 15
Min Max Min Max Min Max Min Max
Unit
A A
mA
IILI IILO
ICC ICC1
mA
ICC2
-
3
-
3
-
3
-
3
mA
Standby Power Supply Current (TTL Level) Standby Power Supply Current (CMOS Level)
ISB ISB1
CE1 = VIH or CE2 = VIL CE1 > Vcc - 0.2V or CE2 < 0.2V, f = 0 VIN < 0.2V or VIN > Vcc- 0.2V IOL = 2 mA IOH = -1 mA
-
0.5 5 1 0.4 -
1.6
0.5 5 1 0.4 -
1.6
0.5 5 1 0.4 -
1.6
0.5 5 1 0.4 -
mA
L LL
1.6
A A
V V
Output Low Voltage Output High Voltage
VOL VOH
Capacitance (f = 1MHz, TA = 250C) Parameter* Symbol
Input Capacitance I/O Capacitance
Test Condition
Vin = 0V Vin = Vout = 0V
Max
7 8
Unit
pF pF
Cin CI/O
* This parameter is guaranteed by device characterization and is not production tested.
AC Test Conditions Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Level
0.4V to 1.6V 5ns 50% of input level (VIL + VIH)/2
TTL
CL *
Output Load Condition 70ns/85 ns CL = 30pf + 1TTL Load Load 100ns/150 ns CL = 100pf + 1TTL Load
Figure A.
* Including Scope and Jig Capacitance
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REV. 1.1 April 2001 V62C1801024L(L)
V62C1801024L(L)
Read Cycle (3,9) (Vcc = 1.8 to 2.2V, Gnd = 0V, TA = 00C to +700C / -400C to +850C) Parameter
Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Output Hold from Address Change Chip Enable to Output in Low-Z Chip Disable to Output in High-Z Output Enable to Output in Low-Z Output Disable to Output in High-Z Power-Up Time Power-Down Time
Symbol
t RC t AA t ACE t OE t OH t CLZ t CHZ t OLZ t OHZ t PU t PD 70 10 10 5 0 -
-70
70 70 40 30 25 70 85 10 10 5 0 -
-85
85 85 40 35 30 85
-100
100 10 10 5 0 100 100 50 40 35 100
-150
150 10 10 5 0 150 150 70 50 40 150
Unit
ns ns ns ns ns ns ns ns ns ns ns
Note
Min Max Min Max Min Max Min Max
4,5 4,5 4,5 4,5 5 5
Write Cycle (3,11) (Vcc = 1.8 to 2.2V, Gnd = 0V, TA = 00C to +700C / -400C to +850C) Parameter
Write Cycle Time Chip Enable to Write End Address Setup to Write End Address Setup Time Write Pulse Width Write Recovering Time Data Valid to Write End Data Hold Time Write Enable to Output in High-Z Output Active from Write End
Symbol
t WC t CW t AW t AS t WP t WR t DW t DH t WZ t OW 70 60 60 0 50 0 30 0 5
-70
-85
-100
-150
Unit
50 ns ns ns ns ns ns ns ns ns ns
Note
Min Max Min Max Min Max Min Max
30 85 70 70 0 60 0 35 0 5 35 100 80 80 0 70 0 40 0 5 40 150 120 120 0 100 0 60 0 5
4,5 4,5
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REV. 1.1 April 2001 V62C1801024L(L)
V62C1801024L(L)
Timing Waveform of Read Cycle 1 (3,6,7,9) (Address Controlled)
tRC
Address
tAA
DOUT
tOH
Data Valid
Timing Waveform of Read Cycle 2 (5,6,8,9) (CE1 Controlled)
tRC CE1 OE tOLZ DOUT tACE tOE tOHZ tCHZ
Data Valid
tCLZ
Supply Current
tPD ICC
50% 50%
tPU
ISB
Timing Waveform of Read Cycle 3 (3,6,8,9) (CE2 Controlled)
tRC CE2 OE tOLZ DOUT tACE tOE tOHZ tCHZ
Data Valid
tCLZ
Supply Current
tPD ICC
50% 50%
tPU
ISB
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REV. 1.1 April 2001 V62C1801024L(L)
V62C1801024L(L)
Timing Waveform of Write Cycle 1
(10,11)
(WE Controlled)
tAW tWC tWR
Address WE
tWP tAS tDW
Data Valid
tDH
DIN
tWZ
DOUT
tOW
Timing Waveform of Write Cycle 2
(10,11)
(CE1 Controlled)
tWC tWR
tAW
Address
tAS
CE1 WE
tCW tWP tWZ tDW tDH
DIN DOUT
Data Valid
Timing Waveform of Write Cycle 3
(10,11)
(CE2 Controlled)
tWC tWR
tAW
Address
tAS
CE2
tCW tWP
WE
tWZ
DIN DOUT
tDW
tDH
Data Valid
REV. 1.1 April 2001 V62C1801024L(L)
7
V62C1801024L(L)
Data Retention Characteristics (L Version Only)(1) Parameter
VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time(2)
Symbol
VDR ICCDR t CDR tR
Test Condition
CE1 > VCC - 0.2V or CE2 < + 0.2V VIN > VCC - 0.2V or V IN < 0.2V
Min
1.0 0 tRC
Max
-
Unit
V A ns ns
1 -
Data Retention Waveform (L Version Only) (TA = 00C to +700C / -400C to +850C)
Data Retention Mode
VCC
Vcc_typ VDR > 1.0V Vcc_typ
tCDR CE
V DR
tR
V IH
V IH
Notes
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. L-version includes this feature. This Parameter is sampled and not 100% tested. For test conditions, see AC Test Condition, Figure A. This parameter is tested with CL = 5pF as shown in Figure B. Transition is measured + 500mV from steady-state voltage. This parameter is guaranteed, but is not tested. WE is HIGH for read cycle. CE1 and OE are LOW and CE2 is HIGH for read cycle. Address valid prior to or coincident with CE1 transition LOW or CE2 transition HIGH. All read cycle timings are referenced from the last valid address to the first transtion address. CE1 or WE must be HIGH or CE2 must be LOW during address transition. All write cycle timings are referenced from the last valid address to the first transition address.
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REV. 1.1 April 2001 V62C1801024L(L)
V62C1801024L(L)
Ordering Information
Device Type* V62C1801024L-70T V62C1801024L-85T V62C1801024L-100T V62C1801024L-150T V62C1801024LL-70T V62C1801024LL-85T V62C1801024LL-100T V62C1801024LL-150T V62C1801024L-70V V62C1801024L-85V V62C1801024L-100V V62C1801024L-150V V62C1801024LL-70V V62C1801024LL-85V V62C1801024LL-100V V62C1801024LL-150V V62C1801024L(L)-70B V62C1801024L(L)-85B V62C1801024L(L)-100B V62C1801024L(L)-150B Speed 70 ns 85 ns 100 ns 150 ns 70 ns 85 ns 100 ns 150 ns 70 ns 85 ns 100 ns 150 ns 70 ns 85 ns 100 ns 150 ns 70 ns 85 ns 100 ns 150 ns 48-fpBGA 8 x 13.4 mm 32-pin Plastic STSOP Package 8 x 20 mm 32-pin Plastic TSOP1
* For Industrial Temperature tested devices, an "I" designator will be added to the end of the device number.
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REV. 1.1 April 2001 V62C1801024L(L)
MOSEL VITELIC
U.S.A.
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V62C1801024L(L)
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(c) Copyright 2001, MOSEL VITELIC Inc.
4/01 Printed in U.S.A.
The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications.
MOSEL VITELIC
3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461

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